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Altera_Forum
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11 years ago

Slack issue in dual clock FIFO

Hi. I have dual clk fifo in my project for Stratix V. Write clk - 250 MHz, read clk - 100 MHz. Fifo has aclr signal that is equal to wr_rst OR rd_rst. wr_rst is synchronous to 250 MHz, rd_rst is s...
Altera_Forum's avatar
Altera_Forum
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11 years ago

hatter: yes, you can cut the path to the synchronizer. Altera doesn't do that just in case you feed it with a reset and the same domain and want it to be timed, but it can be cut.

kaz: I'm not sure I follow what you mean about the D input to the counter. The counter is not enabled to increment since all reads are disabled, so it doesn't matter what is at the D input since it will be ignored.