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Altera_Forum
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11 years ago

Slack issue in dual clock FIFO

Hi. I have dual clk fifo in my project for Stratix V. Write clk - 250 MHz, read clk - 100 MHz. Fifo has aclr signal that is equal to wr_rst OR rd_rst. wr_rst is synchronous to 250 MHz, rd_rst is s...
Altera_Forum's avatar
Altera_Forum
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11 years ago

1) That seems wrong, as the internal counters should be reset by the reset circuitry generated by your settings.

2) Technically, the read side of the FIFO is usually a don't care as far as Recovery/Removal analysis. The reason is that the read logic doesn't change out of reset because the FIFO is empty. The only condition where it could be a problem is if you disabled the read protection circuitry and were issuing a read at the same time you come out of reset, which I've never seen done and seems like a bad idea all around.