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Altera_Forum
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7 years ago

SISO testbench and waveform HELP

Hello, i am new to VHDL and i want some directions. I want to make a Serial in serial out 4 bit shift register, but my waveforms in output have some red marks as you can see below. https://alter...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

SOUT is an output from the UUT. Therefore the UUT sets the value of Sout. If it is always 0, then there is a problem with the UUT, or th way you're driving the UUT.

The X values occur because you are driving '1' against the value of '0' from the UUT.

I also notice you are generating enable like a clock. and therefore likely never actually enabling the UUT. It needs to be set for full clock cycles, not half cycles.