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Altera_Forum
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8 years ago

SISO testbench and waveform HELP

Hello, i am new to VHDL and i want some directions. I want to make a Serial in serial out 4 bit shift register, but my waveforms in output have some red marks as you can see below. https://alter...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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You're driving Sout in the testbench, and the UUT is also driving Sout. Only the UUT should be driving SOut.

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You mean i should not change the values of Sout in the process? When i do it Sout is always 0.