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Altera_Forum
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8 years ago

Single multiplier takes up a whole DSP block for

Hello, I'm using a Cyclone V SOC FPGA. Currently my design has 8 multipliers (which I coded in VHDL instead of instantiating). The inputs to the multipliers are 12 and 16 bits wide. ...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Can you show the VHDL code? Have you tried instantiating the multipliers from the IP Catalog instead of using code inference?