Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

simulation problems:Warning: (vsim-3473) Component instance "i1 : ex1" is not bound.

hi everyone: i build a simple project, use schematic as top, when i want to simulate the project, the modelsim shows: Warning: (vsim-3473) Component instance "i1 : ex1" is not bound. Time: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

actually the test bench is *.vht(*.vt for verilog) even if i use vhd(or verilog) as top, the way i generate the test bench is processing=>start=>start test bench template writer

if find a way to fix the problem: let the quartus generate a vhd file for the sch, then delete the sch file, make the vhd file as the top, then simulate...