Simulation issues and integration Quartus with Active-HDL

Hi,

my system contains FFT megacore and UART. System has to receive 16 bit data (bulit from two 8 bit UART frames each), buffer it and process the data through FFT core. I have some problems with simulation in Quartus, because even functional simulation (2 ms) takes three hours (Celeron M 1,7 GHz, 2 GB DDR2 RAM 667MHz). At this stage of design I need quick, functional simulation to determine whether blocks in my system are synchronized correctly. How can I accelerate simulation ?

And another question, have anyone tried to use Active-HDL with IP mega cores libraries ?