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Hi,
Your problem is "SOME" of the pins are not visible in node finder.
If you are going for timing simulation then internal signals may not appear in the node finder. To see how they function you can go for functional simulation for which you will have to do generate functional simulation netlist. If you want to see them in timing simulation you have to define them as as input/output signal for testing purposes.
Another option is in the node finder filter instead of selecting Pins(All) select Design Entry (All Names). They can be customized also.
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Hi,
are all of your ports missing ? Did you get any messages like "input stuck to GND" during the synthesis ? That could be a hint that you have an error in your source code and the block is removed during synthesis.
Kind regards
GPK
Honored Contributor
