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Altera_Forum's avatar
Altera_Forum
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14 years ago

Simulation Error

Hi, all:

I encoutered a problem --- when I do RTL simualtion, it shows a warning:

Warning : Invalid transition to 'X' detected on PLL input clk. This edge will be ignored.

Time: 0 Instance: Test_vlg_vec_tst.i1.ClkConv.altpll_component.pll0.n1

Error: (vsim-3601) Iteration limit reached at time 0 ps.

I just have an initial block to simulate the external clock input. So what's the problem. Please give me some clues. Thank you very much!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Check that you don't have two sources for the pll input clock, such as two different processes.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi, Daixiwen:

    Thanks for the reply. I found the error was caused by the unit of timescale. I change 1ps to 1ns, and the error vanished.