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MCost7's avatar
MCost7
Icon for New Contributor rankNew Contributor
7 years ago

Simulation behavior didn't match with synthesized design

The quartus version 18.1 is used, the target FPGA is Stratix IV. The code that is not correctly synthesized is: assign addr = (sel1 & sel2) ? (dst == 3'b001) : (dst == 3'b000); But the simul...
Pvand1's avatar
Pvand1
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

I'm not really familiarwith Verilog, but it seems to me the second part is only equal to the first part when dst = 3'b000

Does your simulion cover all the cases?

Do you have timing issues?

I might have missed deleted comments but I don't see anything about a quartus report that the above posts mentions.