Altera_Forum
Honored Contributor
15 years agoSimulating schematic with Altera custom function
Dear all,
sorry for disturbing but I always have problems with these TTL compatible blocks. I've a simple design composed of a schematic bdf file including the 74148 component taken from the others/maxplus 2 library. The design compiles well. When I run the RTL simulation I get a complain regarding missing HDL files in the project. If I try to convert the bdf in HDL code, in order to add it to the project, I get many errors. The first one being: Design file contains illegal characters for Verilog HDL. When I run the Gate Level simulation I get an error for not loaded design. I also filed a SR with no answer from Altera. The project file is attached. Thx in advance.