Honored Contributor
Honored ContributorI also guess it has something to do with instantiation of VHDL stuff in the generated Verilog files. But the files are encrypted, I have no idea how to change this. We thought about implementing Verilog wrappers for all our components - I guess that would match the Qsys philosophy perfectly :o . Maybe it is the simplest solution for the problem with this very component but in the end we will spend time working around language problems, so I am not convinced. We have done two projects with sopc_builder where everything worked out alright so why change? If qsys on the other hand lacks proper mixed-language support we will never be happy with it.
