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Altera_Forum
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14 years ago

Simulating QSYS design with a DDR3 controller

Hi, I am having problems simulating a QSYS design with a DDR3 controller with UniPHY. I try to run a simulation by running the generated msim_setup.tcl. Compilation works as expected, but whe...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I had problems with the mixed language stuff also... i had to change altera's source code instantiation in verilog...