Simulating QSYS design with a DDR3 controller

I have tried without our custom Avalon-MM compliant cache (see this issue http://www.alteraforum.com/forum/showthread.php?t=32304 ) and the complete system in Verilog and it works, so I guess something is wrong with mixed-language designs.

I will go back to sopc_builder now. We have paid much money for a mixed-language simulation license and we are VHDL guys, if we can't use the license now and lose even more time on the project because everybody has to learn Verilog the project is dead.

I'm really p***ed off with that Qsys stuff by now.