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Altera_Forum
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7 years ago

Simulating Cyclone V altera_hps with ModelSim

Quartus 18.0 Standard, ModelSim Intel FPGA Starter Edition 10.5b. Trying to simulate a design that contains a Platform Designer generated instance of altera_hps (for access to HPS-side DDR3 RAM...
Altera_Forum's avatar
Altera_Forum
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7 years ago

FWIW, it does load if I don't use AXI bridges and stick to f2h_sdram0_data declared as an Avalon-MM slave.

It does not really work though. The read request goes out, "waitrequest" is asserted, and the response never arrives. There is a ton of debug messages about precharging and refreshing banks in the console, so, at least it tries to simulate the RAM.