Simulating Altera components

Hi all,

I have to test some Altera components in the "black-box" way (stimulating inputs and analyzing outputs) which are void of architecture, but only have the porting declaration.

for example:

 
component lcell
port (
   a_in : in std_logic;
   a_out : out std_logic);
end component;

How can I do?

Thanks to all.