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Altera_Forum's avatar
Altera_Forum
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10 years ago

Simulating a design, developed using OpenCL

Hi,

I am totally a newbie on this, so pardon me if I ask any dumb questions.

Suppose I design a simple adder using OpenCL then how I do simulate it. Like, may be I am not sure in my design that which signal is getting asserted at what time. So is there any way I can simulate and observe the results before putting my design on FPGA ?

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  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The altera OpenCL environment has an emulator, if you search the altera documentation you should be able to find the way to run the emulator. This is only a functional emulator and runs rather slow, but it (mostly) does its job.