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AndyRea's avatar
AndyRea
Icon for New Contributor rankNew Contributor
4 years ago

simulate parameterized ip block dcfifo_mixed_widths

using this as a verilog module included in a design inside a vhdl wrapper, how do i get modelsim to pick up the dcfifo_mixed_widths ip block properly so it can run testbenches? // synopsys tran...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi,

Since there are no feedback for this thread, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you.

Thanks,

Best regards,
Sheng