Simualtion of test benches

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Hi everyone,

I have written some basic programs using VHDL for multiplexers, adders and others, I have simulated all of them and have got desired results. I just want to know if anybody can help me ''how can I simulate and get the waveform of the test benches and which software I need to use '' i shall be thankful

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Hi,

first of all, how did you simulate your design without using a simulation tool ?

Do you plan to use Altera FPGA's for your design ? As far as I know there is a Web

edition of the Mentor "Modelsim" simulator available on the Altera homepage. It includes

a waveform viewer.

Kind regards

GPK

hi,

thanks for your concern, well i have used that simulator i mean quartus II tool, now i need to simulate test benches, so i dont know how and which software tool gonna simulate test benches for the same, as u said there is mentor modelsim available so does it support test benches in vhdl or not? i shall be very thankfull

Modelsim is a proper VHDL / verilog simulator - yes, it will simulate your VHDL testbenches.

A proper simulator handles VHDL and doesn't care which bits of it happen to be synthesisable as it does not do synthesis.

When you sign up for your Quartus web edition licence you have to select whether or not you want the Modelsim licence included with it. If you have licensing problems then double check what box you ticked.

Note that Modelsim is one simulator of many. It's free for Altera with the web edition licence.

GHDL is also a free simulator and is open-source. Its language support is very good and in some cases better than the commercial simulators.

If you're going to spend money on a simulator then I wouldn't personally recommend Modelsim - ActiveHDL from Aldec is much better.