simple VHDL program --> need help please

first debounce significantly your 'sig' signal : very quite easy to write with other process with counter

* that counts to a fixed value if no 'sig' event happens

* that be cleared if a 'sig' event happens.

For example, clk is 20ns-periode (50MHz) and you want to not consider pulse < 100us. So counter for this will count to (100us/20ns = 5000) if no event happens.

Just little but important corrections here :

process (reset, clk)
   variable detect : STD_ULOGIC_VECTOR(1 downto 0);
   -- variable count : UNSIGNED(8 downto 0); -- not used here
begin
if reset= '1' then
   detect := "00";
   counter <= (others => '0');
   arrived <= '0';
   final_sig <= '0';
   sig1 <= '0';
   sig2 <= '0';
   count_flag<= (others => '0');
elsif rising_edge(CLK) then
   sig1 <= sig;
   sig2 <= sig1;
   final_sig <= sig2;
   -- rising_edge <= sig2 and not(final_sig); -- one way to detect rising_edge
   -- count_flag<= count_flag+1;
   -- if(count_flag > 3) then
   detect(1) := detect(0); -- other way to detect edges
   detect(0) := sig2 ; -- sig2 only !!
   if (detect = "01") or (detect = "10") then -- detecting rising edge or falling edge
      if (counter < req_dist(8 downto 1)) then
         counter <= counter + 1;
      else
         arrived <= '1';
         counter <= (others => '0');
         count_flag<= (others => '0');
      end if;
   end if;
   -- end if;
   end if;
end process;