simple VHDL program --> need help please

[ code]...[ /code]

thats what i done : (its does not work , still the same situation ... maybe the incoming signal ("sig") is bouncing like you sayed...)

what do you suggest to try ?

process (reset, clk)

variable detect : STD_ULOGIC_VECTOR(1 downto 0);

variable count : UNSIGNED(8 downto 0);

begin

if reset= '1' then

detect := "00";

counter <= (others => '0');

arrived <= '0';

final_sig <= '0';

sig1 <= '0';

sig2 <= '0';

count_flag<= (others => '0');

elsif rising_edge(CLK) then

sig1 <= sig;

sig2 <= sig1;

final_sig <= sig2;

-- rising_edge <= sig2 and not(final_sig);

-- count_flag<= count_flag+1;

-- if(count_flag > 3) then

detect(1) := detect(0);

detect(0) := sig2 and not(final_sig); -- sig after 2 DFF to avoid metastibility

if (detect = "01") or (detect = "10") then -- detecting rising edge or falling edge

if (counter < req_dist(8 downto 1)) then

counter <= counter + 1;

else

arrived <= '1';

counter <= (others => '0');

count_flag<= (others => '0');

end if;

end if;

-- end if;

end if;

end process;