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Altera_Forum's avatar
Altera_Forum
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13 years ago

simple VHDL program --> need help please

i have an external asynchronious signal (called "sig") which i have to count its rising or falling edges. i wrote a program which somehow ends very quickly --> after 2 rising edges, req_dist = 32 -->...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

i can really see the metastabillity situation in signal tap.

i understood how to implement a rising/falling edge by "detect" variable. but how do i combine 2 DFF to this program ?

very appriciate your help !