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Altera_Forum's avatar
Altera_Forum
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13 years ago

simple VHDL program --> need help please

i have an external asynchronious signal (called "sig") which i have to count its rising or falling edges. i wrote a program which somehow ends very quickly --> after 2 rising edges, req_dist = 32 -->...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi,

Please Quote your code with [ code]...[ /code]

You don't need "use ieee.std_logic_arith.all;" 

if(req_dist /= "0") then

req_dist is a vector, i don't know how it is interpreted.

Maybe you have metastability events. Put at least 2 D-FlipFlop on your signal "sig".

Quite complicated to count signal edges.

I suggest (not complete) : 


     process (reset, clk)
      variable detect      : STD_ULOGIC_VECTOR(1 downto 0);
      variable count       : UNSIGNED(8 downto 0);
   begin
      if reset_n = '1' then
         detect := "00";
         count := 0;
          arrived <= '0';
         
      elsif rising_edge(clk) then
            
            detect(1) := detect(0);
            detect(0) := sig; -- sig after 2 DFF to avoid metastibility
         
            if (detect = "01") or (detect = "10") then -- detecting rising edge or falling edge
               
               if count < req_dist(8 downto 1) then 
                  count := count + 1;
               else
                  arrived <= '1';
                  counter <= (others => '0');             
               
            end if; 
      end if;
   end process;