Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

SignalTap logging to external memory?

Hi, Is it possible to get SignalTap to use external memory for data logging? I got 256MByte of DDR2 memory in my NIOS system, using the Altera DDR2 memory controller. Logging traces to t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

jakobjones:

Yes, it was exactly that I wanted, captures which are of lower bandwide (compared to internal FPGA RAM), but with long sequences of signals.

If Altera had/made an IP that plug'ed on to the Avalon bus as a busmaster on one side, and to "probe-signals" on the other, any free bandwide on whatever RAM on the Avalon bus that is present, could be used for logging.

Doing the IP myself, will still miss the important integration with the SignalTap GUI in Quartus on the PC, so although making a FIFO+Avalon master DMA muck-up would not be a big problem, getting the data out of the RAM and presented on the PC in a usefull way would need some work, I think?

Hope Altera will do such a core/GUI integration one day.

/Peter