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Moreover, there are still unconstrained inputs ... is it correct ? In this design there are 4 inputs (2 buttons, 1 switch, 1 clock) and all input ports are present in .SDC.
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Run "Report Ignored Constraints" command in TimeQuest to see if all your SDC commands are accepted.
After running "Report Unconstrained Paths" check which actual ports are unconstrained (In Report window see Unconstrained Paths -> Setup Analysis -> Unconstrained Input Ports or Unconstrained Output Ports). This way you will find out which ports are left unconstrained or there is some error in your SDC file.
I am guesing that you will find that those two input ports are altera_reserved_tdi and altera_reserved_tms. You can also use set_false_path for those ports. For JTAG i use:
create_clock -period "10 MHz" -name altera_reserved_tck [get_ports altera_reserved_tck]
set_false_path -from [get_ports {altera_reserved_tdi}]
set_false_path -from [get_ports {altera_reserved_tms}]
set_false_path -to [get_ports {altera_reserved_tdo}]
# Specify the JTAG clock in a group
set_clock_groups -asynchronous -group altera_reserved_tck
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How to properly setup "Report Metastability" in TimeQuest in order to get reliable overview of metastability issues. Actually when I run "Report Metastability", the "non-calculated" value is filled everywhere in the report
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I think you have to set Synchronizer identification option to AUTO in Settings -> TimeQuest Timing Analyzer.
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The metastability issue can be only managed with "design-related" means (e.g. add synchronization flip-flops in the verilog-coded module just after input ports, and then apply thy synchronizer outputs to state machine) or there are some options in Quartus, that allow to do it automatically (e.g. specify in some way a particular input port as port that requires synchronization). In this regard Assignment Editor could be evoked: the Assignment Name column has a collection of different values, including, for example, Synchronizer Identification. So, resuming ... the synchronization chain can be added only in VHDL/Verilog or also via some option in Assignment Editor ?
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Yes synchronization chain can be added only in VHDL/Verilog. Synchronizer Identification option prevents synchronization chain from optimizations and enables MTBF analysis.
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