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As mentioned, use false paths for switches and LEDs. altera_reserved_tck is the JTAG clock. You don't need to constrain this.
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Hello,
Here is the last version of
.sdc file (if I correctly understood the suggestion):
create_clock -name clk -period 20.000 derive_clock_uncertainty# set_input_delay -clock { clk } 5 # set_input_delay -clock { clk } 5 # set_input_delay -clock { clk } 5
set_false_path -from
set_false_path -from
set_false_path -from
Unfortunately it didn't help: input signal on
sw port puts the "state machine" in undefined state.
Moreover, there are still unconstrained inputs ... is it correct ? In this design there are 4 inputs (2 buttons, 1 switch, 1 clock) and all input ports are present in
.sdc.
http://www.alteraforum.com/forum/attachment.php?attachmentid=13257&stc=1 Are there some options that I could add into
.sdc file in order to proceed with full timing analysis ?
Concerning metastability issue, that could be the cause of problem, I have a couple of questions:
- How to properly setup "Report Metastability" in TimeQuest in order to get reliable overview of metastability issues. Actually when I run "Report Metastability", the "non-calculated" value is filled everywhere in the report
- The metastability issue can be only managed with "design-related" means (e.g. add synchronization flip-flops in the verilog-coded module just after input ports, and then apply thy synchronizer outputs to state machine) or there are some options in Quartus, that allow to do it automatically (e.g. specify in some way a particular input port as port that requires synchronization). In this regard assignment editor could be evoked: the Assignment Name column has a collection of different values, including, for example, synchronizer identification. So, resuming ... the synchronization chain can be added only in VHDL/Verilog or also via some option in assignment editor ?
Thanks
Honored Contributor
