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Hi,
I did not read all your posts but from firts glance you have timing related problems. First try to synchronize your SW signal to clk domain with a two-stage shift-register only then feed it to state machine. You can add state machine states in signaltap by clicking right mouse button and chossing "Add state machine nodes.."
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Thanks for suggestion.
This example I took from this book:
https://www.amazon.com/embedded-design-processor-verilog-examples/dp/1118011031/ref=sr_1_1?s=books&ie=utf8&qid=1487338380&sr=1-1&keywords=embedded+sopc+design+with+nios+ii+processor+and+verilog+examples So, undoubtedly, it was tested ... although the reference card in this book was
altera de1 based on a cyclone ii ep2c20, and I use
terasic de1 soc, I don't think that it could make impact on the code functionality.
Concerning states of
state machine, they are already added in SignalTap ... at least you can see "zero" and "wait1" on the waveforms ... until the moment when state machine "crashes" for some unexplained reasons. At that moment the state of the state machine is displayed as
0.
For the moment I'm trying to understand what does "input constraint" mean with respect to an input that is driven by an external switch.
Honored Contributor
