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You need a base clock constraint, create_clock, in your .sdc file for the design, as well as any related I/O timing constraints using set_input_delay and set_output_delay.
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Here is the content of the .SDC file:
create_clock -name clk -period 20.0 clk
derive_pll_clocks
derive_clock_uncertainty
Concerning I/O timing constraints, I din't find how to setup them ... in the
quartus prime standard edition handbook, vol. 3, "Timing Constraints" chapter there is very few information on this topic.
In my design there are (except clock) only 3 inputs: 2 buttons and 1 switch and 4x7 outputs (4 7-segment displays).
Is there some information how to setup such staff.
Anyway, here is the content of the TimeQuest "Unconstrained Paths Summary":
https://www.alteraforum.com/forum/attachment.php?attachmentid=13242 Apparently the luck of the input constraints still prevents the design to work correctly. Here is SignalTap simulation result - the state machine changes its state from "wait1" to NOSTATE (blue line marker) without any visible cause: the state machine "follows" the
sw signal, but as you can state, the sw is constant when state changes from "wait1" to NOSTATE.
https://www.alteraforum.com/forum/attachment.php?attachmentid=13243 Thanks
P.S. Also there is a strange clock
altera_reserved_tck (that I didn't specified) in the clock list .
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