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Honored Contributor
Honored ContributorSignalTap II issue
Hello, Here is debounce state machine: module debounce_explicit(input clk, reset, sw, output reg db_level, db_tick); //symbolic state declaration
localparam
zero = 2'b...
Altera_ForumHonored Contributor
Honored ContributorUnless otherwise specified by synthesis attribute, the state machine is coded in default "one hot" style, the state is represented by four register bits. Respectively the state machine can fall into illegal states. This can happen if the input signals to the state machine involve timing violations, e.g. asynchronous external signals. Instead of "one hot" you get zero or multiple hot state bits. At worst case, the state machine may be stuck in such an illegal state.
I don't remember how an illegal state is shown in signal tap, but I expect it has no symbolic name. You should either care that the timing violation is fixed or if this isn't possible under all circumstances, specify safe state machine logic that recovers automatically from illegal states.
