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Altera_Forum
Honored Contributor
11 years agoSignaltap: discontinuty length in conditional traces
Is it possible to get signaltap to show a true timeline when conditional storage is enabled? I'm trying to track down some issues with latency on PCIe requests (which can take 256+ clocks at th...
Altera_Forum
Honored Contributor
11 years ago --- Quote Start --- It might all be down to some very dodgy looking PCIe cabling. The board doesn't plug directly into a PCIe socket, but it connected by two 'SATA' cables connected header board plugged into the PCIe socket. --- Quote End --- Sounds like my kind of hardware setup :) (I use PCIe to SMA breakout cables from SAMTEC) Can you try running a transceiver toolkit test? You do not need a PRBS pattern generator at the other end, just traffic ... I'm pretty sure you can run TTK over a valid PCIe link, but I have not tried to do that. --- Quote Start --- And the 40 minute build times don't help the rate of debugging (on a i7 with 8GB memory running Ubuntu). --- Quote End --- Ha! I hear you on that one ... I script my long compiles so that I can walk away while my machine builds multiple designs ... but that does not help when debugging! Cheers, Dave