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Altera_Forum's avatar
Altera_Forum
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10 years ago

Signaltap: discontinuty length in conditional traces

Is it possible to get signaltap to show a true timeline when conditional storage is enabled? I'm trying to track down some issues with latency on PCIe requests (which can take 256+ clocks at th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

It might all be down to some very dodgy looking PCIe cabling.

The board doesn't plug directly into a PCIe socket, but it connected by two 'SATA' cables connected header board plugged into the PCIe socket.

And the 40 minute build times don't help the rate of debugging (on a i7 with 8GB memory running Ubuntu).