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Yes, I've no problem writing unix (various) kernel code and device drivers.
So verifying/exercising the dma and pcie is relatively easy.
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Ok.
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The failure rate seems to depend on the pattern of pcie transfers - changing the buffer size of my 'reflect data' test (actually reflect over my hdlc link as well) changes the error rate.
I'm going to see if the 'test_out' signals show anything interesting.
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If you were to use two PCIe end-points; one as the PCIe master and the other as the PCIe slave, you would be able to SignalTap II both ends of the PCIe transaction. If you had say an external 1pps signal or a trigger signal, you could use that to start a counter synchronously on both boards. If that counter was part of your traces, then you'd be able to compare the transactions on the two boards. Not sure if it'll help, but at least you'd have better visibility into both ends of the design ...
The other option would be to buy one of the SoC kits that has a PCIe slot and put your FPGA board in that. In that case, you could trace the root-complex and end-point.
Good luck with your debugging! :)
Cheers,
Dave
Honored Contributor
