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Altera_Forum's avatar
Altera_Forum
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10 years ago

Signaltap: discontinuty length in conditional traces

Is it possible to get signaltap to show a true timeline when conditional storage is enabled? I'm trying to track down some issues with latency on PCIe requests (which can take 256+ clocks at th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Yes, I've no problem writing unix (various) kernel code and device drivers.

So verifying/exercising the dma and pcie is relatively easy.

The failure rate seems to depend on the pattern of pcie transfers - changing the buffer size of my 'reflect data' test (actually reflect over my hdlc link as well) changes the error rate.

I'm going to see if the 'test_out' signals show anything interesting.