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Altera_Forum
Honored Contributor
11 years agoSignaltap: discontinuty length in conditional traces
Is it possible to get signaltap to show a true timeline when conditional storage is enabled? I'm trying to track down some issues with latency on PCIe requests (which can take 256+ clocks at th...
Altera_Forum
Honored Contributor
11 years ago --- Quote Start --- In our case the linux driver on the x86 host is simple enough anyway. It supports: 1) pread/pwrite through to the fpga BAR space. 2) mmap() of both BAR space and the fpga's PCIe master window (allocating physmem as needed). --- Quote End --- In the case of using DMA on the FPGA board, you need to reserve some memory to DMA into or from. I've written simple drivers for the x86 that allocate memory and print the physical address to the dmesg buffer. You can then manually program DMA controller registers to move data to/from the board. I'm pretty sure the code is in here (for an older kernel, so might need tweaking) https://www.ovro.caltech.edu/~dwh/correlator/pdf/cobra_driver.pdf https://www.ovro.caltech.edu/~dwh/correlator/software/cobra_driver.tar.gz --- Quote Start --- Also I didn't think PCIe supported transfers between two endpoints. --- Quote End --- I'm pretty sure you can. The root-complex BIOS/bootloader sets up the PCIe bus addresses. If you program a PCIe end-point with host addresses that correspond to another PCIe end-point, the DMA will go from the end-point to the PCIe switch (or root-complex) over to the destination PCIe end-point. As far as software is concerned, it should work just like PCI. :) Cheers, Dave