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Altera_Forum's avatar
Altera_Forum
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11 years ago

Signaltap: discontinuty length in conditional traces

Is it possible to get signaltap to show a true timeline when conditional storage is enabled? I'm trying to track down some issues with latency on PCIe requests (which can take 256+ clocks at th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

In our case the linux driver on the x86 host is simple enough anyway.

It supports:

1) pread/pwrite through to the fpga BAR space.

2) mmap() of both BAR space and the fpga's PCIe master window (allocating physmem as needed).

There might be some suitable status info on the fpga - but it is a bit thin!

Also I didn't think PCIe supported transfers between two endpoints.