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It all works 'most of the time', the root-complex is an intel atom board.
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Sorry to hear that, that makes it really hard to debug.
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PCIe read bursts usually take 128-256 clocks depending on the actual length.
Writes are all posted and only have a delay of about 8 clocks + the data transfer clocks.
I've have to write a simple multi-channel dma controller to generate the burst transfers.
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If your PCIe setup allows you to plug in two of your end-point devices, then it might be easier to setup DMA transfers between the two end-points, rather than the end-point to root-complex.
I've used this scheme to debug PCI boards. Eg., I'll put the PowerPC processor on the PCI peripheral boards in reset, and then from the x86 host memmap the PCI board registers, program the DMA controller of one board to transfer to the other, and then read/write to the memory on the PowerPC board. This saves having to write a custom driver, and is "low-level" enough for me to know what is exactly happening.
You could do much the same thing ...
Cheers,
Dave
Honored Contributor
