Signaltap: discontinuty length in conditional traces

It all works 'most of the time', the root-complex is an intel atom board.

PCIe read bursts usually take 128-256 clocks depending on the actual length.

Writes are all posted and only have a delay of about 8 clocks + the data transfer clocks.

I've have to write a simple multi-channel dma controller to generate the burst transfers.