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Altera_Forum's avatar
Altera_Forum
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11 years ago

Signaltap: discontinuty length in conditional traces

Is it possible to get signaltap to show a true timeline when conditional storage is enabled? I'm trying to track down some issues with latency on PCIe requests (which can take 256+ clocks at th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I traced a 32bit clock counter.

The discrepency is 2156000 counts of the 62.5MHz 'application' clock.

I make that 34.5ms - far longer than I ever imagined.

So I don't think they can be 'normal' latency issues.

I can only imagine that something like a PCIe retrain has happened.