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Honored Contributor
Honored ContributorSignalTap - II question
problem: Unable to view certain internal registers in SignalTap II i've tried this (added this to my verilog file). i still don't see any of these registers/wire in signaltap. //one att...
Altera_ForumHonored Contributor
Honored Contributor1. I need to understand what these different steps do and how I can use is it to save time (Design to get it working on FPGA). Let me see if I can find info in manual.
2. In the attached image any idea why "state_read" shows up as nice neat 3 width register but "state_write" is just not recognizable. How do I make "state_write" show up as neat 3 bit register?
