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Altera_Forum's avatar
Altera_Forum
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12 years ago

Signals in Testbench

Hi, This might be very easy question but I'm new to FPGA. I have a signal which is called "tx_busy_s" with an initial value '0'. But this signal comes as "U" in the simulation. I use...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thank you for your help. I've made some changes according to your explanation and it works.