Signal Tap logic analyser issue

The LE and RAM resources consumed by SignalTap II are precisely listed in the SignalTap window. As long as the design can be succesfully compiled, there should be no problem. Compile times usually increases when resources run short, also timing closure possibly becomes more difficult.

The reported problems are clearly of a different kind. Getting "Instance not found" repeatedly normally means, that the FPGA has been configured with a different design than that containing the SignalTap II instance.

In some cases, JTAG signal integrity issues prevent correct SignalTap operation although the design can be (mostly) configured correctly. Additional interferences emitted by the design in operation are the most popular reason for this behaviour. But SignalTap II error messages are different in this case, if I remember right.