Forum Discussion
Altera_Forum
Honored Contributor
12 years agosignaltap much be connected to a clock, and you can set it to trigger on a certain condition. Could you not just set it to wait until the counter is 0? if it doesnt capture enough time you will need to re-compile with a larger window.
You can also set up multiple cores inside the design and have them trigger at different points. If you need some more complicated trigger conditions, it is much easier to generate the trigger logic in HDL, use syn_keep and noprune attributes on them and then connect them into signaltap.