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hcom's avatar
hcom
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Signal Tap example from Intel training course always fails timing

I was told to re-post this question because it didn't get resolved after 2 months: I am using Quartus Prime 21.1.0 Build 169 03/24/2021 SC Pro Edition to target a Cyclone 10 GX (10CX085) FPGA. I ...
  • Nurina's avatar
    Nurina
    4 years ago

    Hi,

    Thanks for bringing this up. This SDC constraints problem was probably missed by the internal team. I'll report this problem to them so they may rectify it.

    Regards,

    Nurina

Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

Thanks for bringing this up. This SDC constraints problem was probably missed by the internal team. I'll report this problem to them so they may rectify it.

Regards,

Nurina