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For debugging my project I use the Signal Tap Logic Analyzer in Quartus II. The time region of interest which I want to see is from the beginning of the first clock cycles. Doing the start of analysis manually, I have no chance to catch this point of time. Is there a possibility to tell the analyzer to start automatically after programming the device?
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Read the SignalTap II documentation and look for power-on triggers. I recall using these to trigger at some point after the FPGA was configured. You can then use JTAG at an arbitrary time later to download the capture traces.
Cheers,
Dave
Honored Contributor
