Should Quartus 18.1 support FF creation by this: Q <= D when rising_edge(CLK); The D and CLK are input ports on a module, and Q is a output port. The Quartus 18.1 breaks with internal error due to this construction.

Thanks for the answer.

It may not be supported coding style for inference of flip-flops, and it is used very little, if at all in practice, so may be OK not to support in Intel coding guidelines.

However, the coding style makes Quartus 18.1 break with internal error, which indicates a bug in the tool.

? Any suggestion for how I can report this bug ?