Shortening NIOSII Simulation run time with FPGA SOC system as recommended in AN351

​Hello,

No I am not using the custom memory models. I am using the generic memory model that is generated by default from the platform designer and simulating the same. Well, I am not really looking for any compiler options to shorten the code. But when I see in model sim simulations, during the boot code execution before jumping to main there is lot of operations performed by the NIOSII data bus on the internal onchip RAM. So my request is: Is there a possibility to remove some operations from the boot code and replace them with initialising the onchip RAM components (Note this is only for simulation purposes). I understand on the FPGA it will be the actual boot code that runs.

Thanks,

Arvind