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Altera_Forum's avatar
Altera_Forum
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12 years ago

shift register structural modeling error with port

Im a beginner in this verilog programing....

i tried to run the shift register with inserted module but there is port missing error...

still couldn't identify the problem and need some help...

need help correctting the codes if there is a problem with it...

thanks.:confused:

[DFF MODULE STRUCTURAL]

module dffstrct(d,clk,q1,q2,w1,w2,w0);

input d;

input clk;

output q1,q2,w1,w2,w0;

not (w0,d);

nand (w1,d,clk);

nand (w2,w0,clk);

nand (q1,w1,q2);

nand (q2,w2,q1);

endmodule

[SHIFT REGISTER INSERTED MODULE]

module shftstrct(c1,c2,c3,c4,d,clk);

input d;

input clk;

output c1,c2,c3,c4;

dffstrct m1(.c1(c1),.c2(c2),.d(d),.clk(clk));

dffstrct m2(.c3(c3),.c4(c4),.d(c1),.clk(clk));

endmodule

[[TESTBENCH]]

module shftstrct_tb();

reg d;

reg clk;

wire c1,c2,c3,c4;

initial begin

d = 0;

clk = 0;

end

always# 50 clk=~clk;

always# 100 d=~d;

initial # 1000 $stop;

shftstrct uut (.c1(c1),.c2(c2),.c3(c3),.c4(c4),.d(d),.clk(clk));

endmodule

[ERROR FOUND]

Loading work.dffstrct# ** Warning: (vsim-3017) C:/altera/91/modelsim_ase/examples/sfhtstrct_tb.v(22): [TFMPC] - Too few port connections. Expected 6, found 4.# Region: /sfhtstrct_tb/uut# ** Error: (vsim-3063) C:/altera/91/modelsim_ase/examples/sfhtstrct_tb.v(22): Port 'q1' not found in the connected module (1st connection).# Region: /sfhtstrct_tb/uut# ** Error: (vsim-3063) C:/altera/91/modelsim_ase/examples/sfhtstrct_tb.v(22): Port 'q2' not found in the connected module (2nd connection).# Region: /sfhtstrct_tb/uut# ** Warning: (vsim-3722) C:/altera/91/modelsim_ase/examples/sfhtstrct_tb.v(22): [TFMPC] - Missing connection for port 'c1'.# ** Warning: (vsim-3722) C:/altera/91/modelsim_ase/examples/sfhtstrct_tb.v(22): [TFMPC] - Missing connection for port 'c2'.# ** Warning: (vsim-3722) C:/altera/91/modelsim_ase/examples/sfhtstrct_tb.v(22): [TFMPC] - Missing connection for port 'c3'.# ** Warning: (vsim-3722) C:/altera/91/modelsim_ase/examples/sfhtstrct_tb.v(22): [TFMPC] - Missing connection for port 'c4'.# ** Warning: (vsim-3017) C:/altera/91/modelsim_ase/examples/sfhtstrct.v(8): [TFMPC] - Too few port connections. Expected 7, found 4.# Region: /sfhtstrct_tb/uut/m1# ** Error: (vsim-3063) C:/altera/91/modelsim_ase/examples/sfhtstrct.v(8): Port 'c1' not found in the connected module (1st connection).# Region: /sfhtstrct_tb/uut/m1# ** Error: (vsim-3063) C:/altera/91/modelsim_ase/examples/sfhtstrct.v(8): Port 'c2' not found in the connected module (2nd connection).# Region: /sfhtstrct_tb/uut/m1# ** Warning: (vsim-3722) C:/altera/91/modelsim_ase/examples/sfhtstrct.v(8): [TFMPC] - Missing connection for port 'q1'.# ** Warning: (vsim-3722) C:/altera/91/modelsim_ase/examples/sfhtstrct.v(8): [TFMPC] - Missing connection for port 'q2'.# ** Warning: (vsim-3722) C:/altera/91/modelsim_ase/examples/sfhtstrct.v(8): [TFMPC] - Missing connection for port 'w1'.# ** Warning: (vsim-3722) C:/altera/91/modelsim_ase/examples/sfhtstrct.v(8): [TFMPC] - Missing connection for port 'w2'.# ** Warning: (vsim-3722) C:/altera/91/modelsim_ase/examples/sfhtstrct.v(8): [TFMPC] - Missing connection for port 'w0'.# ** Warning: (vsim-3017) C:/altera/91/modelsim_ase/examples/sfhtstrct.v(9): [TFMPC] - Too few port connections. Expected 7, found 4.# Region: /sfhtstrct_tb/uut/m2# ** Error: (vsim-3063) C:/altera/91/modelsim_ase/examples/sfhtstrct.v(9): Port 'c3' not found in the connected module (1st connection).# Region: /sfhtstrct_tb/uut/m2# ** Error: (vsim-3063) C:/altera/91/modelsim_ase/examples/sfhtstrct.v(9): Port 'c4' not found in the connected module (2nd connection).# Region: /sfhtstrct_tb/uut/m2# ** Warning: (vsim-3722) C:/altera/91/modelsim_ase/examples/sfhtstrct.v(9): [TFMPC] - Missing connection for port 'q1'.# ** Warning: (vsim-3722) C:/altera/91/modelsim_ase/examples/sfhtstrct.v(9): [TFMPC] - Missing connection for port 'q2'.# ** Warning: (vsim-3722) C:/altera/91/modelsim_ase/examples/sfhtstrct.v(9): [TFMPC] - Missing connection for port 'w1'.# ** Warning: (vsim-3722) C:/altera/91/modelsim_ase/examples/sfhtstrct.v(9): [TFMPC] - Missing connection for port 'w2'.# ** Warning: (vsim-3722) C:/altera/91/modelsim_ase/examples/sfhtstrct.v(9): [TFMPC] - Missing connection for port 'w0'.# Error loading design

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    The errors are caused by wrong module instantiation statements 

    dffstrct m1(.c1(c1),.c2(c2),.d(d),.clk(clk));
dffstrct m2(.c3(c3),.c4(c4),.d(c1),.clk(clk));

    Either a typo or misunderstanding of required syntax. The dffstrct output ports to be connected are q1 and q2.

    Secondly, dffstrct doesn't model a D flip-flop as required for a shift register, it's a D latch with enable.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    The errors are caused by wrong module instantiation statements 

    dffstrct m1(.c1(c1),.c2(c2),.d(d),.clk(clk));
dffstrct m2(.c3(c3),.c4(c4),.d(c1),.clk(clk));

    Either a typo or misunderstanding of required syntax. The dffstrct output ports to be connected are q1 and q2.

    Secondly, dffstrct doesn't model a D flip-flop as required for a shift register, it's a D latch with enable.

    --- Quote End ---

    so, to create d flip flop i need to do as the attachment by using dffstrct with latch enable...

    but i still not so sure about the connection in verilog...

    please correct these:

    module shftstrct(d,w1,q,q_bar,clk);

    input d;

    input clk;

    output w1,q,q_bar;

    not (clk,clk_bar);

    dffstrct m1(.q1(w1),.d(d),.clk(clk_bar));

    dffstrct m2(.q1(q),.q2(q_bar),.clk(clk),.d(w1));

    endmodule

    and need help in doing the testbench....
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    The module connection seems correct at first sight. Also the master-slave design looks good.

    Please consider that the circuit is only reasonable as an excercise problem solution, but not a reasonable way to implement a programmable logic design. Here a hardware DFF primitive would be the lowest level building block in a structural design.