shift register inferring

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Hi,

I have a design which uses shift registers. But in the compilation report that memory is only inferred as normal register (I followed the format of inferring shift register). Moreover I had a shift register successfully inferred at a different part of my design using the same format.

Below is the way I inferred shift register but failed

typedef struct {
    float vector;
 
} vec;
typedef struct {
    
    vec lane_data;
} input_lane;
some_kernel() {
    input_lane data_in;
    input_lane weight_in;
    //more than one loop(nested)
    for(......) {
        ......
       # pragma unroll
        for(uint j = TILE_SIZE - 1; j > 0; j--) {
            data_shift_reg = data_shift_reg;
            weight_shift_reg = weight_shift_reg;
        }
        ......
    }
}

I feel like in Altera OpenCL memory type some times don't get to be what I desired, and its type depends on the its position in the kernel (for example in which level of nested loops).

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Quartus has default freedom of choosing ram or registers for shift registers unless you override locally (through attributes)or globally through project settings to stop inferring rams.

Hi,

Thanks for your reply!

I know I can force BRAM and register. Is there any way to force shift register?

by stopping quartus from inferring ram for shift register you are inferring registers for shift registers. Reread my previous post, it is not about inferring ram for ram.

There are two structures here: ram or register. There is no third structure of shift register block.

Shift register means you want to shift data and happened to retain its name as register but can be implemented in registers or ram block to save registers population from annihilation.

similarly you can implement ram in registers or in ram blocks.

and you can implement registers in registers or in ram blocks and even in fabric lut logic (as a latch) if it gets too dry.

But if vendors want to add dedicated shift register block then it is their choice