Sharing of signals over different processes in modelsim not working as expected ?

1. That is because enable_clock is set to '1' after the first falling edge of the clock, and it remains at '1'.

The thrid process (main_data_gen) is waiting for enable_clock to toggle to '1' after the second clock. But it already at '1', and hence waits forever.

Wait until is triggered by a 'event on the sensitivy list (the signals you are waiting for).

the workaround is to do this:

if enable_clock /= '1' then
  wait until enable_clock = '1';
end if;

2. Now to comment on the code. Why are you manually waiting for edges on the clock? VHDL has the build in functions rising/falling_edge, so its usually much better to use those on the code, and is more readable. in addition, use loops to wait for a defined number of clocks:

for i in 1 to 10 loop  -- wait for 10 clocks
  wait until rising_edge(clk);
end loop;

or even better, in some tools package, define a procedure to wait for a specified number of clocks (its a pretty standard thing to want to do in any testbench:

procedure wait_for_clks( constant n   :    integer;
                         signal   clk : in std_logic ) is
begin
  for i in 1 to n loop
    wait until rising_edge(clk);
  end loop;
end procedure;
 
.......
 
process
begin
  ......
  wait_for_clks(10, clk);
end process;

3. Next, if you want a process to halt, putting wait until 0=1; will wait forever, but its a fairly nonsense piece of code. Why not simply write "wait", as a single wait will wait forever

stim_proc : process
begin
  ....do something
  wait_for_clks(10, clk);
  .. do something else
  wait;    -- waits forever;
end process;

4. For the PSD_data_table, why not set the values in an initialisation function, rather than assign them in a process?