setup and hold time with set_input_delay

sstrell is correct that the first thing is to distinguish source synchronous vs system synchronous.

For set_input_delay, the key point is that it describes the external data arrival window at the FPGA input pin, relative to the reference clock edge. It is not “remaining internal time after subtracting board clock delay.”

For a true source-synchronous interface, common clock/data PCB delay usually cancels, so what matters is mostly:

• upstream device Tco(min/max)
• clock/data board skew
• jitter/uncertainty

A common model is:

• set_input_delay -max = Tco_max + data_trace - clock_trace
• set_input_delay -min = Tco_min + data_trace - clock_trace 
• refer to https://docs.altera.com/v/u/docs/653688/an-433-constraining-and-analyzing-source-synchronous-interfaces

So if data and clock traces are matched, the trace delay does not magically give the FPGA extra internal time.

Also, set_output_delay on the transmitting chip and set_input_delay on the receiving chip are related, but they are not redundant. One constrains the transmitter against receiver requirements; the other constrains the receiver against transmitter behavior.